Adders & Subtractors

How digital hardware performs arithmetic — from adding two single bits to subtracting multi-bit numbers using two's complement.

Digital LogicElectrical Engineering Year 2Free preview
⏱️ About 16 min

A processor adds millions of numbers per second — but at the gate level, every one of those additions starts with a circuit that can barely handle the number 1 + 1.

💡
The big idea: Binary addition decomposes into a cascade of simple logic gates: XOR for the sum bit, AND for the carry. Chain enough of these together and you can add or subtract numbers of any width.
🎯 By the end, you'll be able to
  • Build a half-adder from XOR and AND gates and explain why it cannot accept a carry-in
  • Extend to a full-adder that handles a carry-in, and derive its sum and carry-out expressions
  • Cascade full-adders into a ripple-carry adder and trace a 4-bit addition stage by stage
  • Perform binary subtraction using two's-complement addition, discarding overflow carry-out
📎 Helpful to know first
  • SOP, POS & Standard Logic Forms

The half-adder: adding two bits

The simplest arithmetic circuit adds two single bits A and B and produces two outputs: a sum bit S and a carry bit C. The sum is 1 when exactly one input is 1 (the XOR), and the carry is 1 only when both inputs are 1 (the AND).

ABS (Sum)C (Carry)
0000
0110
1010
1101

This circuit is called a half-adder because it has no input for a carry coming in from a lower bit position. It works for the least-significant bit, but every higher position needs to account for a possible carry from below.

\[ S = A \oplus B \]
Sum bit of a half-adder: 1 when inputs differ.
\[ C = A \cdot B \]
Carry bit of a half-adder: 1 only when both inputs are 1.

The full-adder: handling carry-in

A full-adder accepts three inputs: the two operand bits A and B, plus a carry-in C_in from the previous stage. The sum is the XOR of all three inputs — it is 1 when an odd number of inputs are 1. The carry-out is the majority function: it is 1 whenever two or more of the three inputs are 1.

\[ S = A \oplus B \oplus C_{in} \]
Full-adder sum: 1 when an odd number of inputs are 1.
\[ C_{out} = AB + C_{in}(A \oplus B) \]
Full-adder carry-out, equivalently the majority function AB + AC_in + BC_in.
📝 Worked example: A full-adder receives A=1, B=1, Cin=1. Find the sum bit S and carry-out Cout.
  1. Sum = A ⊕ B ⊕ Cin = 1 ⊕ 1 ⊕ 1 = 0 ⊕ 1 = 1.
  2. Cout = AB + Cin(A ⊕ B) = (1·1) + 1·(1 ⊕ 1) = 1 + 1·0 = 1 + 0 = 1.
  3. The result bits are Cout=1, S=1, giving binary '11' = 3, which matches 1 + 1 + 1 = 3.
✓ Sum = 1, Carry-out = 1 (result '11' = 3, matching 1+1+1).

Ripple-carry adder: cascading for multi-bit addition

To add two n-bit numbers, we chain n full-adders together. The carry-out of each stage feeds directly into the carry-in of the next. The least-significant stage takes Cin = 0 (or a dedicated initial carry). Because the carry ripples leftward through each stage in sequence, this architecture is called a ripple-carry adder. It is simple to build but slow for wide words — the final sum is not valid until the carry has propagated through every stage.

📝 Worked example: Trace a 4-bit ripple-carry adder computing A = 0101 (5) + B = 0011 (3) with Cin = 0. Bits are indexed LSB-first: A0A1A2A3 = 1,0,1,0 and B0B1B2B3 = 1,1,0,0.
  1. Stage 0 (bit 0): A0=1, B0=1, Cin=0 → S0 = 1⊕1⊕0 = 0, carry C1 = 1.
  2. Stage 1 (bit 1): A1=0, B1=1, Cin=1 → S1 = 0⊕1⊕1 = 0, carry C2 = 1.
  3. Stage 2 (bit 2): A2=1, B2=0, Cin=1 → S2 = 1⊕0⊕1 = 0, carry C3 = 1.
  4. Stage 3 (bit 3): A3=0, B3=0, Cin=1 → S3 = 0⊕0⊕1 = 1, carry C4 = 0.
  5. Result: S3S2S1S0 = 1000 = 8, with final carry-out C4 = 0 (no overflow). This matches 5 + 3 = 8.
✓ Sum = 1000 (8 in decimal), carry-out = 0. Matches 5 + 3 = 8 with no overflow.
✏️ Practice: A 4-bit ripple-carry adder computes 0011 (3) + 0110 (6) with Cin = 0. What is the decimal value of the 4-bit sum?
Solution
  1. 3 + 6 = 9, which fits in 4 bits (max unsigned = 15).
  2. LSB-first bit values: A0=1, A1=1, A2=0, A3=0 (from 0011); B0=0, B1=1, B2=1, B3=0 (from 0110).
  3. Stage 0: A0=1, B0=0, Cin=0 → S0 = 1⊕0⊕0 = 1, C1 = 0.
  4. Stage 1: A1=1, B1=1, Cin=0 → S1 = 1⊕1⊕0 = 0, C2 = 1.
  5. Stage 2: A2=0, B2=1, Cin=1 → S2 = 0⊕1⊕1 = 0, C3 = 1.
  6. Stage 3: A3=0, B3=0, Cin=1 → S3 = 0⊕0⊕1 = 1, C4 = 0.
  7. Sum = S3S2S1S0 = 1001 = 9, carry-out = 0.

Subtraction via two's complement

Subtraction in digital hardware is typically performed by adding the two's complement of the subtrahend. For an n-bit number B, the two's complement is ~B + 1, where ~B inverts every bit. Then A − B = A + (~B + 1), and any carry-out beyond the n-bit width is simply discarded. This elegant trick means the same adder circuit handles both addition and subtraction — the only extra hardware is a bank of inverters and a way to feed Cin = 1 into the LSB stage.

📝 Worked example: Compute A − B = 0101 (5) − 0011 (3) using 4-bit two's-complement addition.
  1. Invert B: ~B = ~0011 = 1100.
  2. Add 1: ~B + 1 = 1100 + 1 = 1101 (this represents −3 in 4-bit two's complement).
  3. Add A + (~B + 1) = 0101 + 1101 = 10010 (5-bit raw result).
  4. Discard the carry-out beyond 4 bits: 10010 → 0010.
  5. Result = 0010 = 2, matching 5 − 3 = 2.
✓ Result = 0010 (2 in decimal). The discarded carry-out (1) is expected and harmless.
✏️ Practice: Using 4-bit two's-complement addition, compute 1010 (10) − 0110 (6). What is the decimal value of the 4-bit result?
Solution
  1. ~B = ~0110 = 1001.
  2. ~B + 1 = 1001 + 1 = 1010 (= −6 in 4-bit two's complement).
  3. A + (~B+1) = 1010 + 1010 = 10100 (5-bit raw result).
  4. Discard carry-out: 10100 → 0100.
  5. 0100 = 4, matching 10 − 6 = 4.

Check your understanding

1. Why is a half-adder insufficient for all bit positions except the LSB in a multi-bit adder?
A half-adder only handles two inputs (A, B) and has no Cin input, so it cannot accept a carry from a lower stage.
2. In a 4-bit ripple-carry adder computing 5 + 3, what is the final carry-out C4?
5 + 3 = 8, which fits in 4 bits (max unsigned = 15), so C4 = 0 (no overflow).
3. When performing A − B via two's-complement addition, what do you do with the carry-out beyond the bit width?
The carry-out beyond n bits is expected and is simply discarded — it is a natural artifact of two's-complement arithmetic.
🔎 Related lessons
Multiplexers & Decoders · soon
✅ Key takeaways
  • A half-adder adds two bits with XOR (sum) and AND (carry) but has no carry-in input.
  • A full-adder adds three inputs (A, B, Cin) with S = A⊕B⊕Cin and Cout = AB + Cin(A⊕B).
  • A ripple-carry adder chains full-adders stage by stage, with each Cout feeding the next Cin.
  • Subtraction is done by adding the two's complement (~B + 1) and discarding any carry-out beyond the bit width.
➡️ Now that we can build arithmetic circuits, the next challenge is routing selected signals — which is exactly what multiplexers and decoders do.
Want to test yourself on this? Try the Electrical Aptitude test →