Latches & Flip-Flops

Inside this lesson

Explain why latches and flip-flops are classified as sequential logic, not combinational
Analyze an SR latch built from cross-coupled NOR gates, including its forbidden input combination
Describe how a D latch eliminates the SR invalid state and what 'transparent' means
Distinguish level-triggered D latches from edge-triggered D flip-flops
Apply the JK flip-flop truth table, including the toggle mode that resolves the SR ambiguity
Derive the T flip-flop as a special case of the JK flip-flop and use its characteristic equation

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Educational content covering topics typical of a first- and second-year electrical engineering curriculum. Not a substitute for accredited coursework, and not suitable for real circuit or system design without review by a licensed professional engineer.